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INTEGRATED CIRCUITS
DATA SHEET
PCF2103 family LCD controllers/drivers
Product specification File under Integrated Circuits, IC12 1998 May 11
Philips Semiconductors
Product specification
LCD controllers/drivers
CONTENTS 1 2 3 4 5 6 7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.4.1 8.4.2 8.4.3 8.5 8.6 8.6.1 8.6.2 8.6.3 FEATURES APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION LCD bias voltage generator Oscillator External clock Power-on reset Power-down mode Registers Busy flag Address Counter (AC) Display Data RAM (DDRAM) Character Generator ROM (CGROM) Character Generator RAM (CGRAM) Cursor control circuit Timing generator LCD row and column drivers Reset function INSTRUCTIONS Clear display Return home Entry mode set I/D S Display control (and partial power-down mode) D C B Cursor or display shift Function set DL (parallel mode only) M H 8.7 8.8 8.9 8.10 8.11 8.12 8.12.1 8.12.2 8.12.3 8.12.4 8.12.5 8.12.6 8.12.7 9 9.1 9.2 9.2.1 9.2.2 9.2.3 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 18 19
PCF2103 family
Set CGRAM address Set DDRAM address Read busy flag and address counter Write data to CGRAM or DDRAM Read data from CGRAM or DDRAM Extended function set instructions and features New instructions Icon control IM IB Screen configuration Display configuration Reducing current consumption INTERFACE TO MICROCONTROLLER Parallel interface I2C-bus interface Characteristics of the I2C-bus I2C-bus protocol Definitions LIMITING VALUES HANDLING DC CHARACTERISTICS AC CHARACTERISTICS TIMING CHARACTERISTICS APPLICATION INFORMATION 8-bit operation, 1-line display using internal reset 4-bit operation, 1-line display using internal reset 8-bit operation, 2-line display I2C-bus operation, 1-line display BONDING PAD LOCATIONS DEFINITIONS LIFE SUPPORT APPLICATIONS PURCHASE OF PHILIPS I2C COMPONENTS
1998 May 11
2
Philips Semiconductors
Product specification
LCD controllers/drivers
1 FEATURES
PCF2103 family
* Single-chip LCD controller/driver * 2-line display of up to 12 characters + 120 icons, or 1-line display of up to 24 characters + 120 icons * 5 x 7 character format plus cursor; 5 x 8 for kana (Japanese syllabary) and user defined symbols * Icon mode: reduced current consumption while displaying icons only(1) * Icon blink function * On-chip: - Generation of intermediate LCD bias voltages - Oscillator requires no external components (external clock also possible) * Display data RAM: 80 characters * Character generator ROM: 240, 5 x 8 characters * Character generator RAM: 16, 5 x 8 characters; 3 characters used to drive 120 icons, 6 characters used if icon blink feature is used in application * 4 or 8-bit parallel bus and 2-wire I2C-bus interface * CMOS compatible * 18 row, 60 column outputs * Mux rates 1 : 18 (for normal operation) and 1 : 2 (for icon-only mode) * Uses common 11 code instruction set (extended) * Logic supply voltage range, VDD - VSS = 1.8 to 5.5 V; chip may be driven with two battery cells * Display supply voltage range, VLCD - VSS = 2.2 to 6.5 V * Very low current consumption (20 to 120 A): - Icon mode: <25 A - Power-down mode: <2.5 A.
(1) Icon mode is used to save current. When only icons
2
APPLICATIONS
* Telecom equipment * Portable instruments * Point-of-sale terminals. 3 GENERAL DESCRIPTION
The PCF2103 family is a low power CMOS LCD controller and driver, designed to drive a dot matrix LCD display of 2 line by 12 or 1 line by 24 characters with 5 x 8 dot format. All necessary functions for the display are provided in a single chip, including on-chip generation of LCD bias voltages, resulting in a minimum of external components and lower system current consumption. The PCF2103 interfaces to most microcontrollers via a 4 or 8-bit bus or via the 2-wire I2C-bus. The chip contains a character generator and displays alphanumeric and kana (Japanese) characters. The letter `X' in PCF2103X characterizes the built-in character set. Various character sets can be manufactured on request.
are displayed, a much lower operating voltage VLCD can be used and the switching frequency of the LCD outputs is reduced. In most applications it is possible to use VDD as VLCD. 4 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF2103EU/2/F2 - chip with bumps in tray DESCRIPTION VERSION -
1998 May 11
3
Philips Semiconductors
Product specification
LCD controllers/drivers
5 BLOCK DIAGRAM
PCF2103 family
handbook, full pagewidth
C1 to C60
R1 to R18
60 BIAS VOLTAGE GENERATOR COLUMN DRIVERS 60 DATA LATCHES 60 SHIFT REGISTER 5 x 12-BIT 5 CURSOR AND DATA CONTROL 5
18 ROW DRIVERS 18 SHIFT REGISTER 18-BIT
VLCD
OSCILLATOR
OSC
VDD
CHARACTER GENERATOR RAM (128 x 5) (CGRAM) 16 CHARACTERS 8
CHARACTER GENERATOR ROM (CGROM) 240 CHARACTERS
VSS
TIMING GENERATOR
T1
8
DISPLAY DATA RAM (DDRAM) 80 CHARACTERS/BYTES 7 ADDRESS COUNTER (AC) 7 7 INSTRUCTION DECODER 7 DISPLAY ADDRESS COUNTER
PD
PCF2103
DATA REGISTER (DR) 8 I/O BUFFER 8 BUSY FLAG INSTRUCTION REGISTER 8 POWER-ON RESET
MGL259
DB0 to DB3/SA0
DB4 to DB7
E
R/W
RS
SCL
SDA
Fig.1 Block diagram.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
6 PINNING SYMBOL VDD OSC PD T1 VSS VLCD R9 to R16 R18 C60 to C1 R8 to R1 R17 SCL SDA E RS R/W DB7 DB6 DB5 DB4 DB3/SA0 DB2 DB1 DB0 Note 1. This is the voltage used for the generation of LCD bias levels. DIE PAD 1 2 3 4 5 6 7 to 14 15 supply voltage oscillator/external clock input power-down pad input test pad (connected to VSS) ground VLCD input; note 1 LCD row driver outputs 9 to 16 LCD row driver output 18 DESCRIPTION
PCF2103 family
16 to 23, 26 to 50, LCD column driver outputs 60 to 1 53 to 77, 80, 81 82 to 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 LCD row driver outputs 8 to 1 LCD row driver output 17 I2C-bus serial clock input I2C-bus serial data input/output data bus clock input register select input read/write input bit of bi-directional data bus bit of bi-directional data bus bit of bi-directional data bus bit of bi-directional data bus bit of bi-directional data bus/I2C-bus address pin bit of bi-directional data bus bit of bi-directional data bus bit of bi-directional data bus
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
Table 1 Pin functions; note 1 FUNCTION register select DESCRIPTION
PCF2103 family
NAME RS
RS selects the register to be accessed for read and write; there is an internal pull-up on this pin RS = 0 selects the instruction register for write and the busy flag and address counter for read RS = 1 selects the data register for both read and write
R/W E
read/write data bus clock
R/W selects either the read (R/W = 1) or write (R/W = 0) operation; there is an internal pull-up on this pin pin E is set HIGH to signal the start of a read or write operation; data is clocked in or out of the chip on the negative edge of the clock the bi-directional, 3-state data bus transfers data between the system controller and the PCF2103; DB7 may be used as the busy flag, signalling that internal operations are not yet completed; in 4-bit operations the 4 higher order lines DB7 to DB4 are used; DB3 to DB0 must be left open-circuit; there is an internal pull-up on each of the data lines these pins output the data for columns these pins output the row select waveforms to the display; R17 and R18 drive the icons positive power supply for the liquid crystal display when the on-chip oscillator is used this pin must be connected to VDD; an external clock signal, if used, is input at this pin input for the I2C-bus clock signal I/O for the I2C-bus data line the hardware sub-address line is used to program the device sub-address for two different PCF2103s on the same I2C-bus must be connected to VSS; not user accessible
DB7 to DB0 data bus
C1 to C60 R1 to R18 VLCD OSC SCL SDA SA0 T1 PD Note
column driver outputs row driver outputs LCD power supply oscillator serial clock line serial data line address pin test pad
power-down pad PD selects chip power-down mode; for normal operation PD = 0
1. When the I2C-bus is used, the parallel interface pin E must be defined as E = 0. In I2C-bus read mode DB7 to DB0 should be connected to VDD or left open-circuit. a) When the parallel bus is used, pins SCL and SDA must be connected to VSS or VDD; they may not be left unconnected. b) If the 4-bit interface is used without reading out from the PCF2103 (i.e. R/W is set permanently to logic 0), the unused ports DB0 to DB3 can either be set to VSS or VDD instead of leaving them open.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
7 7.1 FUNCTIONAL DESCRIPTION LCD bias voltage generator
PCF2103 family
The intermediate bias voltages for the LCD display are generated on-chip. This removes the need for an external resistive bias chain and significantly reduces the system current consumption. The optimum value of VLCD depends on the multiplex rate, the LCD threshold voltage (Vth) and the number of bias levels and is given by the relationships given in Tables 2 and 3. Using a 5-level bias scheme for 1 : 18 maximum rate allows VLCD <5 V for most LCD liquids. Table 2 Optimum/maximum values for VOP (off pixels start darkening; Voff = Vth) NUMBER OF LEVELS 5 3 Von/Vth 1.272 2.236 VOP/Vth 3.7 2.283 VOP (typical; for Vth = 1.4 V) 5.2 V 3.9 V
MUX RATE 1 : 18 1:2 Table 3
Minimum values for VOP (on pixels clearly visible; Von > Vth) NUMBER OF LEVELS 5 3 Von/Vth 1.12 1.2 VOP/Vth 3.2 1.5 VOP (typical; for Vth = 1.4 V) 4.6 V 2.1 V
MUX RATE 1 : 18 1:2 7.2 Oscillator
The on-chip oscillator provides the clock signal for the display system. No external components are required and pin OSC must be connected to VDD. 7.3 External clock
During power-down, the whole chip is being reset and will restart with a clear display after power-down. Therefore, the whole chip has to be initialized after a power-down as after an initial power-up. 7.6 Registers
If an external clock is to be used, it is input at the OSC pin. The resulting display frame frequency is given by f osc f frame = -----------3072 Only in the power-down state is the clock allowed to be stopped (OSC connected to VSS), otherwise the LCD is frozen in a DC state. 7.4 Power-on reset
The on-chip power-on reset block initializes the chip after power-on or power failure. This is a synchronous reset and requires 3 oscillator cycles to be executed. Afterwards, a clear display is initiated. 7.5 Power-down mode
The PCF2103 has two 8-bit registers, an Instruction Register (IR) and a Data Register (DR). The Register Select signal (RS) determines which register will be accessed. The instruction register stores instruction codes such as `display clear' and `cursor shift', and address information for the Display Data RAM (DDRAM) and Character Generator RAM (CGRAM). The instruction register can be written from but not read by the system controller. The data register temporarily stores data to be read from the DDRAM and CGRAM. When reading, data from the DDRAM or CGRAM corresponding to the address in the instruction register is written to the data register prior to being read by the `read data' instruction. 7.7 Busy flag
The chip can be put into power-down mode where all static currents are switched off (no internal oscillator, no bias level generation, all LCD outputs are internally connected to VSS) when PD = 1.
The busy flag indicates the internal status of the PCF2103. Logic 1 indicates that the chip is busy and further instructions will not be accepted. The busy flag is output at pin DB7 when RS = 0 and R/W = 1. Instructions should only be written after checking that the busy flag is logic 0 or waiting for the required number of cycles.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
7.8 Address Counter (AC) 7.11
PCF2103 family
Character Generator RAM (CGRAM)
The address counter assigns addresses to the DDRAM and CGRAM for reading and writing and is set by the commands `set CGRAM address' and `set DDRAM address'. After a read/write operation the address counter is automatically incremented or decremented by 1. The address counter contents are output to the bus (DB6 to DB0) when RS = 0 and R/W = 1. 7.9 Display Data RAM (DDRAM)
Up to 16 user defined characters may be stored in the CGRAM. Some CGRAM characters (see Fig.14) are also used to drive icons (6 if icons blink and both icon rows are used in application; 3 if no blink but both icon rows are used in application; 0 if no icons are driven by the icon rows). The CGROM and CGRAM use a common address space, of which the first column is reserved for the CGRAM (see Fig.6). Figure 7 shows the addressing principle for the CGRAM. 7.12 Cursor control circuit
The DDRAM stores up to 80 characters of display data represented by 8-bit character codes. RAM locations which are not used for storing display data can be used as general purpose RAM. The basic RAM-to-display addressing scheme is shown in Fig.2. With no display shift the characters represented by the codes in the first 24 RAM locations starting at address 00 in line 1 are displayed. Figures 3 and 4 show the display mapping for right and left shift respectively. When data is written to or read from the DDRAM wrap-around occurs from the end of one line to the start of the next line. When the display is shifted each line wraps around within itself, independently of the others. Thus all lines are shifted and wrapped around together. The address ranges and wrap-around operations for the various modes are shown in Table 4. 7.10 Character Generator ROM (CGROM)
The cursor control circuit generates the cursor (underline and/or cursor blink as shown in Fig.5) at the DDRAM address contained in the address counter. When the address counter contains the CGRAM address the cursor will be inhibited. 7.13 Timing generator
The timing generator produces the various signals required to drive the internal circuitry. Internal chip operation is not disturbed by operations on the data buses. 7.14 LCD row and column drivers
The PCF2103 contains 18 row and 60 column drivers, which connect the appropriate LCD bias voltages in sequence to the display in accordance with the data to be displayed. R17 and R18 drive the icon rows. The bias voltages and the timing are selected automatically when the number of lines in the display is selected. Figures 8, 9 and 10 show typical waveforms. Unused outputs should be left unconnected.
The Character Generator ROM (CGROM) generates 240 character patterns in 5 x 8 dot format from 8-bit character codes. Figure 6 shows the character set that is currently implemented.
Table 4
Address space and wrap-around operation ADDRESS SPACE 00H to 4FH 00H to 27H; 40H to 67H READ/WRITE WRAP-AROUND(1) 4FH to 00H 27H to 40H; 67H to 00H DISPLAY SHIFT WRAP-AROUND(2) 4FH to 00H 27H to 00H; 67H to 40H
MODE 1 x 24 2 x 12 Notes
1. Moves to next line. 2. Stays within line.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth
display position DDRAM address
non-displayed DDRAM addresses 12345
00 01 02 03 04
22 23 24
15 16 17 18 19 4C 4D 4E 4F
1-line display non-displayed DDRAM address 12345
00 01 02 03 04
10 11 12
09 0A 0B 0C 0D 24 25 26 27
line 1
DDRAM address
12345
40 41 42 43 44
10 11 12
49 4A 4B 4C 4D 64 65 66 67
MGE991
line 2
2-line display
Fig.2 DDRAM-to-display mapping: no shift.
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
14 15 16
4F 00 01 02 03
1-line display 1 DDRAM address 23 4 5 10 11 12
08 09 0A
27 00 01 02 03
line 1
1
23
4
5
10 11 12
48 49 4A
MGE992
67 40 41 42 43
line 2
2-line display
Fig.3 DDRAM-to-display mapping: right shift.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
display handbook, halfpage position DDRAM address
1
23
4
5
22 23 24
16 17 18
01 02 03 04 05
1-line display 1 DDRAM address 23 4 5 10 11 12
0A 0B 0C
01 02 03 04 05
line 1
1
23
4
5
10 11 12
4A 4B 4C
MGE993
41 42 43 44 45
line 2
2-line display
Fig.4 DDRAM-to-display mapping: left shift.
cursor 5 x 7 dot character font alternating display
MGA801
cursor display example
blink display example
Fig.5 Cursor and blink display examples.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth upper
lower 4 bits xxxx
4 bits
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
0000
1
xxxx
0001
2
xxxx
0010
3
xxxx
0011
4
xxxx
0100
5
xxxx
0101
6
xxxx
0110
7
xxxx
0111
8
xxxx
1000
9
xxxx
1001
10
xxxx
1010
11
xxxx
1011
12
xxxx
1100
13
xxxx
1101
14
xxxx
1110
15
xxxx
1111
16
MGD689
Fig.6 Character set `E' in CGROM.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
character handbook, full pagewidth codes (DDRAM data) 7 6 5 4 3 2 1 lower order bits 0 0 0 0 0 0 0 6 5
CGRAM address 4 3 2 1 lower order bits 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 higher order bits
character patterns (CGRAM data) 4 3 2 1 0 4
character code (CGRAM data) 3 2 1 0
higher order bits 0 0 0
higher order bits 0 0
lower order bits 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 character pattern example 2 0 0 0 0 character pattern example 1 cursor position 1 1 1 1 1 1 1 0 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 0 1 0 1 0 1 0 1 0 0 0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
MGE995
0 0 0 0
0 0 0 0
0 0 0 0
0 0 0 0
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
1 1 1 1
0 0 1 1
0 1 0 1
Character code bits 0 to 3 correspond to CGRAM address bits 3 to 6. CGRAM address bits 0 to 2 designate the character pattern line position. The 8th line is the cursor position and display is performed by logical OR with the cursor. Data in the 8th position will appear in the cursor position. Character pattern column positions correspond to CGRAM data bits 0 to 4, as shown in Fig.6. As shown in Figs 6 and 7, CGRAM character patterns are selected when character code bits 4 to 7 are all logic 0. CGRAM data = logic 1 corresponds to selection for display. Only bits 0 to 5 of the CGRAM address are set by the `set CGRAM address' command. Bit 6 can be set using the `set DDRAM address' command in the valid address range or by using the auto-increment feature during CGRAM write. All bits 0 to 6 can be read using the `read busy flag and address counter' command; see Table 7.
Fig.7 Relationship between CGRAM addresses and data and display patterns.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth
frame n
frame n + 1
state 1 (ON) state 2 (OFF)
R1 R2 R3 R4 R5
ROW 1
VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VLCD V2 V3/V4 V5 VSS VOP
R6 R7 R8 R9
ROW 9
ROW 2
COL1
COL2
0.5VOP 0.25VOP state 1 0 V -0.25VOP -0.5VOP -VOP VOP 0.5VOP 0.25VOP state 2 0 V -0.25VOP -0.5VOP -VOP
MGE996
123
18 1 2 3
18
Fig.8 Typical LCD waveforms; character mode.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth
frame n
frame n + 1 only icons are driven (MUX 1 : 2)
VLCD ROW 17 2/3 1/3 VSS
VLCD ROW 18 2/3 1/3 VSS
VLCD ROW 1 to 16 2/3 1/3 VSS
VLCD COL 1 ON/OFF 2/3 1/3 VSS
VLCD COL 2 OFF/ON 2/3 1/3 VSS
VLCD COL 3 ON/ON 2/3 1/3 VSS
VLCD COL 4 OFF/OFF 2/3 1/3 VSS
MGE997
Fig.9 Mux 1 : 2 LCD waveforms; icon mode.
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth V PIXEL
frame n
frame n + 1 state 1 (ON)
state 1 COL 1 ROW 17
VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP 0 -1/3 VOP -2/3 VOP -VOP VOP 2/3 VOP 1/3 VOP
state 2 (OFF)
R17 R18 R1-16
state 3 (OFF)
state 2 COL 2 ROW 17
state 3 COL 1 0 ROW 1 to 16 -1/3 VOP -2/3 VOP -VOP
MGE998
VON(rms) = 0.745 VOP. VOFF(rms) = 0.333 VOP. V ON D = ------------- = 2.23 V OFF
Fig.10 Mux 1 : 2 LCD waveforms; icon mode.
1998 May 11
15
Philips Semiconductors
Product specification
LCD controllers/drivers
7.15 Reset function
PCF2103 family
The PCF2103 automatically initializes (resets) when power is turned on. The reset executes a `clear display' instruction, requiring 165 oscillator cycles. After the reset the chip has the state shown in Table 5. Table 5 STEP 1 2 3 State after reset INSTRUCTION clear display entry mode set display control I/D = 1 S=0 D=0 C=0 B=0 4 function set DL = 1 M=0 H=0 5 6 7 8 +1 (increment) no shift display off cursor off cursor character blink off 8-bit interface 1-line display normal instruction set RESET STATE (BIT/REGISTER) RESET STATE (DESCRIPTION)
default address pointer to DDRAM; the Busy Flag (BF) indicates the busy state (BF = 1) until initialization ends; the busy state lasts 2 ms; the chip may also be initialized by software; see Tables 16 and 17 icon control display/screen configuration I2C-bus interface reset IM, IB = 00 L, P, Q = 000 icons/icon blink disabled default configurations
1998 May 11
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Philips Semiconductors
Product specification
LCD controllers/drivers
8 INSTRUCTIONS
PCF2103 family
In normal use, instructions that perform data transfer with internal RAM are used most frequently. However, automatic incrementing by 1 (or decrementing by 1) of internal RAM addresses after each data write lessens the microcontroller program load. The display shift in particular can be performed concurrently with display data write, enabling the designer to develop systems in minimum time with maximum programming efficiency. During internal operation, no instruction other than the `read busy flag and address counter' instruction will be executed. Because the busy flag is set to logic 1 while an instruction is being executed, the user should verify that the busy flag is at logic 0 before sending the next instruction or wait for the maximum instruction execution time, as given in Table 7. An instruction sent while the busy flag is logic 1 will not be executed.
Only two PCF2103 registers, the Instruction Register (IR) and the Data Register (DR) can be directly controlled by the microcontroller. Before internal operation, control information is stored temporarily in these registers to allow interface to various types of microcontrollers which operate at different speeds or to allow interface to peripheral control ICs. The format for instructions when I2C-bus control is used is shown in Table 6. The PCF2103 operation is controlled by the instructions given in Table 7 together with their execution time. Details are explained in subsequent sections. Instructions are of 4 types, those that: 1. Designate PCF2103 functions such as display format, data length, etc. 2. Set internal RAM addresses 3. Perform data transfer with internal RAM 4. Others. Table 6 Instruction set for I2C-bus commands CONTROL BYTE Co RS Note 1. R/W is set together with the slave address. 0 0 0 0 0 0
COMMAND BYTE
I2C-BUS COMMANDS
DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 note 1
1998 May 11
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LCD controllers/drivers
INSTRUCTION H = 0 or 1 NOP Function set
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
REQUIRED CLOCK CYCLES
0 0
0 0
0 0
0 0
0 1
0 DL
0 0
0 M
0 0
0 H
no operation sets interface Data Length (DL) and number of display lines (M); extended instruction set control (H) reads the Busy Flag (BF) indicating internal operating is being performed and reads address counter contents reads data from CGRAM or DDRAM writes data from CGRAM or DDRAM
3 3
Read busy flag and address counter Read data Write data H=0 Clear display Return home
0
1
BF
AC
0
1 1
1 0
read data write data
3 3
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 0
0 1
1 0
clears entire display and sets DDRAM address 0 in address counter sets DDRAM address 0 in address counter; also returns shifted display to original position; DDRAM contents remain unchanged sets cursor move direction and specifies shift of display; these operations are performed during data write and read sets entire display on/off (D), cursor on/off (C) and blink of cursor position character (B); D = 0 (display off) puts chip into power-down mode moves cursor and shifts display without changing DDRAM contents sets CGRAM address; bit 6 is to be set by the command `set DDRAM address'; look at the description of the commands sets DDRAM address
165 3
Entry mode set
0
0
0
0
0
0
0
1
I/D
S
3
Display control
0
0
0
0
0
0
1
D
C
B
3
Cursor/display shift Set CGRAM address Set DDRAM address
0 0
0 0
0 0
0 1
0
1
S/C
R/L
0
0
3
PCF2103 family
ACG
3
Product specification
0
0
1
ADD
3
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LCD controllers/drivers
INSTRUCTION H=1 Reserved Screen configuration Display configuration Icon control Reserved Reserved Reserved Note 1. X = don't care.
RS
R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
DESCRIPTION
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 1
0 0 0 0 0 1 X
0 0 0 0 0 X X
0 0 0 0 1 X X
0 0 0 1 X X X
0 0 1 IM X X X
0 1 P IB X X X
1 L Q 0 X X X
do not use set screen configuration set display configuration set icon mode (IM), icon blink (IB) do not use do not use do not use
PCF2103 family
Product specification
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 8 BIT I/D S D C B S/C R/L DL H L (ignored, if M = 1) decrement display freeze display off cursor off cursor character blink off: character at cursor position does not blink cursor move left shift 4 bits use basic instruction set left/right screen: standard connection (as in PCF2114); 1st 12 characters of 24: columns are from 1 to 60; 2nd 12 characters of 24: columns are from 1 to 60 column data: left to right (as in PCF2116); column data is displayed from 1 to 60 row data: top to bottom (as in PCF2116); row data is displayed from 1 to 16 and icon row data is in 17 and 18 character mode; full display icon blink disabled 1-line by 24 display last control byte; see Table 6 Specification of mnemonics used in Table 7 LOGIC 0 increment display shift display on cursor on
PCF2103 family
LOGIC 1
cursor character blink on: character at cursor position blinks display shift right shift 8 bits use extended instruction set left/right screen: mirrored connection (as in PCF2116); 1st 12 characters of 24: columns are from 1 to 60; 2nd 12 characters of 24: columns are from 60 to 1 column data: right to left; column data is displayed from 60 to 1 row data: bottom to top; row data is displayed from 16 to 1 and icon row data is in 18 and 17 icon mode; only icons displayed icon blink enabled 2-line by 12 display another control byte follows after data/command
P Q
IM IB M C0
1998 May 11
20
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
RS
R/W
E
DB7
IR7
IR3
BF
AC3
DR7
DR3
DB6
IR6
IR2
AC6
AC2
DR6
DR2
DB5
IR5
IR1
AC5
AC1
DR5
DR1
DB4
IR4 instruction write
IR0
AC4
AC0
DR4
DR0
busy flag and address counter read
data register read
MGA804
Fig.11 4-bit transfer example.
RS
R/W
E
internal
internal operation
DB7
IR7
IR3
busy
AC3
not busy
AC3
D7
D3
instruction write
busy flag check
busy flag check
instruction write
MGA805
IR7 and IR3: instruction 7th and 3rd bit. AC3: address counter 3rd bit. D7 and D3: data 7th and 3rd bit.
Fig.12 An example of 4-bit data transfer timing sequence.
1998 May 11
21
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
RS
R/W
E
internal
internal operation
DB7
data instruction write
busy busy flag check
busy busy flag check
not busy busy flag check
data instruction write
MGA806
Fig.13 Example of busy flag checking timing sequence.
8.1
Clear display
8.3 8.3.1
Entry mode set I/D
`Clear display' writes character code 20H into all DDRAM addresses (the character pattern for character code 20H must be a blank pattern), sets the DDRAM address counter to logic 0 and returns display to its original position if it was shifted. Thus, the display disappears and the cursor or blink position goes to the left edge of the display. Sets entry mode I/D = 1 (increment mode). S of entry mode does not change. The instruction `clear display' requires extra execution time. This may be allowed by checking the Busy Flag (BF) or by waiting until the 165 clock cycles have elapsed. The latter must be applied where no read-back options are foreseen, as in some Chip-On-Glass (COG) applications. 8.2 Return home
When I/D = 1 (0) the DDRAM or CGRAM address increments (decrements) by 1 when data is written into or read from the DDRAM or CGRAM. The cursor or blink position moves to the right when incremented and to the left when decremented. The cursor underline and cursor character blink are inhibited when the CGRAM is accessed. 8.3.2 S
`Return home' sets the DDRAM address counter to logic 0 and returns display to its original position if it was shifted. DDRAM contents do not change. The cursor or blink position goes to the left of the first display line. I/D and S of entry mode do not change.
When S = 1, the entire display shifts either to the right (I/D = 0) or to the left (I/D = 1) during a DDRAM write. Thus it looks as if the cursor stands still and the display moves. The display does not shift when reading from the DDRAM, or when writing into or reading out of the CGRAM. When S = 0 the display does not shift.
1998 May 11
22
Philips Semiconductors
Product specification
LCD controllers/drivers
8.4 8.4.1 Display control (and partial power-down mode) D
PCF2103 family
The Address Counter (AC) content does not change if the only action performed is shift display, but increments or decrements with the `cursor shift'. 8.6 8.6.1 Function set DL (PARALLEL MODE ONLY)
The display is on when D = 1 and off when D = 0. Display data in the DDRAM are not affected and can be displayed immediately by setting D to logic 1. When the display is off (D = 0) the chip is in partial power-down mode: * The LCD outputs are connected to VSS * Bias generator is turned off. 3 oscillator cycles are required after sending the `display off' instruction to ensure all outputs are at VSS, afterwards OSC can be stopped. If the oscillator is running during partial power-down mode (`display off') the chip can still execute instructions. Even lower current consumption is obtained by inhibiting the oscillator (OSC = VSS). To ensure IDD < 2 A the parallel bus pins DB7 to DB0 should be connected to VDD; RS and R/W to VDD or left open-circuit and PD to VDD. Recovery from power-down mode: put PD back to logic 0, if necessary put OSC back to VDD and send a `display control' instruction with D = 1 to enable the display again. 8.4.2 C
Sets interface data width. Data is sent or received in bytes (DB7 to DB0) when DL = 1 or in two nibbles (DB7 to DB4) when DL = 0. When 4-bit width is selected, data is transmitted in two cycles using the parallel bus. In a 4-bit application DB3 to DB0 should be left open-circuit (internal pull-ups). Hence in the first `function set' instruction after power-on N and H are set to logic 1. A second `function set' must then be sent (2 nibbles) to set N and H to their required values. `Function set' from the I2C-bus interface sets the DL bit to logic 1. 8.6.2 M
Chooses either 1-line by 24 display (M = 0) or 2-line by 12 display (M = 1). 8.6.3 H
The cursor is displayed when C = 1 and inhibited when C = 0. Even if the cursor disappears, the display functions I/D, etc. remain in operation during display data write. The cursor is displayed using 5 dots in the 8th line (see Fig.5). 8.4.3 B
When H = 0 the chip can be programmed via the standard 11 instruction codes used in the PCF2116 and other LCD controllers. When H = 1 the extended range of instructions will be used. These are mainly for controlling the display configuration and the icons. 8.7 Set CGRAM address
The character indicated by the cursor blinks when B = 1. The cursor character blink is displayed by switching between display characters and all dots on with a period of f osc approximately 1 s, with f BLINK = --------------52224 The cursor underline and the cursor character blink can be set to display simultaneously. 8.5 Cursor or display shift
`Set CGRAM address' sets bits 5 to 0 of the CGRAM address ACG into the address counter (binary A[5] to A[0]). Data can then be written to or read from the CGRAM. Attention: the CGRAM address uses the same address register as the DDRAM address and consists of 7 bits (binary A[6] to A[0]). With the `set CGRAM address' command, only bits 5 down to 0 are set. Bit 6 can be set using the `set DDRAM address' command first, or by using the auto-increment feature during CGRAM write. All bits 6 to 0 can be read using the `read busy flag and address counter' command. When writing to the lower part of the CGRAM, ensure that bit 6 of the address is not set (e.g. by an earlier DDRAM write or read action).
`Cursor/display shift' moves the cursor position or the display to the right or left without writing or reading display data. This function is used to correct a character or move the cursor through the display. In 2-line displays, the cursor moves to the next line when it passes the last position (40) of the line. When the displayed data is shifted repeatedly all lines shift at the same time; displayed characters do not shift into the next line. 1998 May 11 23
Philips Semiconductors
Product specification
LCD controllers/drivers
8.8 Set DDRAM address 8.12 8.12.1
PCF2103 family
Extended function set instructions and features NEW INSTRUCTIONS
`Set DDRAM address' sets the DDRAM address ADD into the address counter (binary A[6] to A[0]). Data can then be written to or read from the DDRAM. 8.9 Read busy flag and address counter
H = 1 sets the chip into alternate instruction set mode. 8.12.2 ICON CONTROL
`Read busy flag and address counter' reads the Busy Flag (BF) and Address Counter (AC). BF = 1 indicates that an internal operation is in progress. The next instruction will not be executed until BF = 0, so BF should be checked before sending another instruction. At the same time, the value of the address counter expressed in binary A[6] to A[0] is read out. The address counter is used by both CGRAM and DDRAM, and its value is determined by the previous instruction. 8.10 Write data to CGRAM or DDRAM
The PCF2103 can drive up to 120 icons. See Fig.14 for CGRAM to icon mapping. 8.12.3 IM
When IM = 0 the chip is in character mode. In character mode characters and icons are driven (mux 1 : 18). When IM = 1 the chip is in icon mode. In icon mode only the icons are driven (mux 1 : 2). 8.12.4 IB
`Write data' writes binary 8-bit data D[7] to D[0] to the CGRAM or the DDRAM. Whether the CGRAM or DDRAM is to be written into is determined by the previous `set CGRAM address' or `set DDRAM address' command. After writing, the address automatically increments or decrements by 1, in accordance with the entry mode. Only bits D[4] to D[0] of CGRAM data are valid, bits D[7] to D[5] are `don't care'. 8.11 Read data from CGRAM or DDRAM
Icon blink control is independent of the cursor/character blink function. When IB = 0 icon blink is disabled. Icon data is stored in CGRAM character 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). When IB = 1 icon blink is enabled. In this case each icon is controlled by two bits. Blink consists of two half phases (corresponding to the cursor on and off phases called even and odd phases hereafter). Icon states for the even phase are stored in CGRAM characters 0 to 2 (3 x 8 x 5 = 120 bits for 120 icons). These bits also define the icon state when the icon blink is not used. Icon states for the odd phase are stored in CGRAM character 4 to 6 (another 120 bits for the 120 icons). When icon blink is disabled CGRAM characters 4 to 6 may be used as normal CGRAM characters.
`Read data' reads binary 8-bit data D[7] to D[0] from the CGRAM or DDRAM. The most recent `set address' command determines whether the CGRAM or DDRAM is to be read. The `read data' instruction gates the content of the Data Register (DR) to the bus while pin E is HIGH. After pin E goes LOW again, internal operation increments (or decrements) the AC and stores RAM data corresponding to the new AC into the DR. It should be noted that there are only three instructions that update the Data Register (DR). These are: * `set CGRAM address' * `set DDRAM address' * `read data' from CGRAM or DDRAM. Other instructions (e.g. `write data', `cursor/display shift', `clear display', `return home') do not modify the data register content.
1998 May 11
24
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 9 Blink effect for icons and cursor character blink EVEN PHASE on block (all on) state 1: CGRAM characters 0 to 2 off
PCF2103 family
PARAMETER Cursor underline Cursor character blink Icons
ODD PHASE normal (display character) state 2: CGRAM characters 4 to 6
handbook, full pagewidth
display:
COL 1 to 5
COL 6 to 10
COL 56 to 60
ROW 17 -
1
2
3
4
5
6
7
8
9
10
56
57
58
59
60
ROW 18 -
61
62
63
64
65
66
67
68
69
70
116 117 118 119 120
MGE999
block of 5 columns
icon no. handbook, full pagewidth
phase
ROW/COL 7 MSB 6
character codes 5 4 3 2 1 0 LSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 MSB 0 0 0
CGRAM address 5 4 3 2 1 0 4
CGRAM data 3 2 1 0 LSB 0 1 1 1 0 1 0 1 1 1 0 0
icon view
LSB MSB 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0
1-5 6-10 11-15
even even even
17/1-5 17/6-10 17/11-15
0 0 0
56-60 61-65
even even
17/56-60 18/1-5
0 0
0 0
0 0
0 0
0 0
0 0
0 0
1 1
0 0
0 0
0 0
1 1
0 1
1 0
1 0
1 1
1 1
1 0
1 0
1 0
116-120 1-5
even odd (blink)
18/56-60 17/1-5
0 0
0 0
0 0
0 0
0 0
0 1
1 0
0 0
0 0
0 1
1 0
0 0
1 0
1 0
1 0
1 0
1 0
1 0
0 0
1 0
116-120
odd (blink)
18/56-60
0
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
MGG001
CGRAM data bit = logic 1 turns the icon on, data bit = logic 0 turns the icon off. Data in character codes 0 to 2 define the icon states when icon blink is disabled or during the even phase when icon blink is enabled. Data in character codes 4 to 6 define the icon state during the odd phase when icon blink is enabled (not used for icons when icon blink is disabled).
Fig.14 CGRAM-to-icon mapping.
1998 May 11
25
Philips Semiconductors
Product specification
LCD controllers/drivers
8.12.5 SCREEN CONFIGURATION 9 9.1
PCF2103 family
INTERFACE TO MICROCONTROLLER Parallel interface
The default value for L is logic 0. In the event of L = 0 the two halves of a split screen are connected in a standard way i.e. column 1/61, 2/62 to 60/120. In the event of L = 1 the two halves of a split screen are connected in a mirrored way i.e. column 1/120, 2/119 to 60/61. This allows single layer PCB or glass layout. 8.12.6 DISPLAY CONFIGURATION
The PCF2103 can send data in either two 4-bit operations or one 8-bit operation and can thus interface to 4-bit or 8-bit microcontrollers. In 8-bit mode data is transferred as 8-bit bytes using the 8 data lines DB7 to DB0. Three further control lines E, RS and R/W are required; see Table 1. In 4-bit mode data is transferred in two cycles of 4 bits each using pins DB7 to DB4 for transaction. The higher order bits (corresponding to DB7 to DB4 in 8-bit mode) are sent in the first cycle and the lower order bits (DB3 to DB0 in 8-bit mode) in the second. Data transfer is complete after two 4-bit data transfers. Note that two cycles are also required for the busy flag check. 4-bit operation is selected by instruction. See Figs 11 to 14 for examples of bus protocol. In 4-bit mode pins DB3 to DB0 must be left open-circuit. They are pulled up to VDD internally.
The default value for P and Q is logic 0. P = 1 mirrors the column data whereas Q = 1 mirrors the row data. 8.12.7 REDUCING CURRENT CONSUMPTION
Reducing current consumption can be achieved by one of the options mentioned in Table 10. Table 10 Reducing current consumption ORIGINAL MODE Character mode Display on ALTERNATIVE MODE icon mode (control bit IM) display off (control bit D)
1998 May 11
26
Philips Semiconductors
Product specification
LCD controllers/drivers
9.2 9.2.1 I2C-bus interface CHARACTERISTICS OF THE I2C-BUS 9.2.2 I2C-BUS PROTOCOL
PCF2103 family
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a Serial Clock Line (SCL). Both lines must be connected to a positive supply via a pull-up resistor. Data transfer may be initiated only when the bus is not busy. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal put on the bus by the transmitter during which time the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges must pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
Before any data is transmitted on the I2C-bus, the device which should respond is addressed first. The addressing is always carried out with the first byte transmitted after the start procedure. The I2C-bus configuration for the different PCF2103 read and write cycles is shown in Figs 20 to 21. The slow down feature of the I2C-bus protocol (receiver holds SCL low during internal operations) is not used in the PCF2103. 9.2.3 DEFINITIONS
* Transmitter: the device which sends the data to the bus * Receiver: the device which receives the data from the bus * Master: the device which initiates a transfer, generates clock signals and terminates a transfer * Slave: the device addressed by a master * Multi-master: more than one master can attempt to control the bus at the same time without corrupting the message * Arbitration: procedure to ensure that, if more than one master simultaneously tries to control the bus, only one is allowed to do so and the message is not corrupted * Synchronization: procedure to synchronize the clock signals of two or more devices.
1998 May 11
27
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
MASTER TRANSMITTER/ RECEIVER SDA SCL
SLAVE RECEIVER
SLAVE TRANSMITTER/ RECEIVER
MASTER TRANSMITTER
MASTER TRANSMITTER/ RECEIVER
MGA807
Fig.15 System configuration.
handbook, full pagewidth
SDA
SCL data line stable; data valid change of data allowed
MBC621
Fig.16 Bit transfer.
handbook, full pagewidth
SDA
SDA
SCL S START condition P STOP condition
SCL
MBC622
Fig.17 Definition of START and STOP conditions.
handbook, full pagewidth
DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER S START condition clock pulse for acknowledgement
MBC602
1
2
8
9
Fig.18 Acknowledgement on the I2C-bus.
1998 May 11
28
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acknowledgement from PCF2103 S
Philips Semiconductors
handbook, full pagewidth
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0 2n 0 bytes
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE
AP
slave address R/W Co
1 byte Co
n 0 bytes update data pointer
MGL250
29
S 011101A0 0 PCF2103 slave address R/W
PCF2103 family
Product specification
Fig.19 Master transmits to slave receiver; write mode.
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11
acknowledgement S
Philips Semiconductors
agewidth
LCD controllers/drivers
S 0 1 1 1 0 1 A 0 A 1 RS CONTROL BYTE A
0
DATA BYTE
A 0 RS CONTROL BYTE A
DATA BYTE(1)
A
slave address R/W Co
2n
0 bytes Co
1 byte
n 0 bytes
acknowledgement
acknowledgement
no acknowledgement
30
S
SLAVE ADDRESS S A1A 0 DATA BYTE A DATA BYTE 1P n bytes R/W Co update data pointer last byte update data pointer
MGG003
PCF2103 family
Product specification
(1) Last data byte is a dummy byte (may be omitted).
Fig.20 Master reads after setting word address; write word address, set RS; `read data'.
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
dbook, full pagewidth
acknowledgement from PCF2103
acknowledgement from master
no acknowledgement from master
S
SLAVE ADDRESS
S A1A 0
DATA BYTE
A
DATA BYTE
1P
n bytes R/W Co update data pointer
last byte update data pointer
MGL251
Fig.21 Master reads slave immediately after first byte; read mode (RS previously defined).
dbook, full pagewidth
SDA
t BUF
t LOW
tf
SCL
t HD;STA
tr
t HD;DAT
t HIGH
t SU;DAT
SDA t SU;STA
MGA728
t SU;STO
Fig.22 I2C-bus timing diagram.
1998 May 11
31
Philips Semiconductors
Product specification
LCD controllers/drivers
10 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VDD VLCD VI(1) VI(2) VO II IO IDD, ISS and ILCD Ptot P/out Tstg 11 HANDLING supply voltage LCD supply voltage input voltage on pins SCL and SDA output voltage on pins R1 to R18, C1 to C60 and VLCD DC input current DC output current VDD, VSS or VLCD current total power dissipation power dissipation per output storage temperature PARAMETER -0.5 -0.5 -0.5 -0.5 -10 -10 -50 - - -65 MIN.
PCF2103 family
MAX. +6.5 +7.5 VDD + 0.5 +6.5 VLCD + 0.5 +10 +10 +50 400 100 +150
UNIT V V V V V mA mA mA mW mW C
input voltage on pins OSC, RS, R/W, E and DB7 to DB0 -0.5
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see "Handling MOS Devices").
1998 May 11
32
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
12 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 to 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL Supplies VDD VLCD ISS supply voltage LCD supply voltage supply current note 1 VDD = 3 V; VLCD = 5 V; notes 1 and 2 icon mode; VDD = 3 V; VLCD = 2.5 V; notes 1 and 2 power-down mode; VDD = 3 V; VLCD = 2.5 V; DB7 to DB0, RS and R/W = 1; OSC = 0; PD = 1; note 1 VPOR Logic VIL LOW-level input voltage on pins T1, E, RS, R/W, DB7 to DB0 and SA0 HIGH-level input voltage on pins T1, E, RS, R/W, DB7 to DB0 and SA0 LOW-level input voltage on pin PD HIGH-level input voltage on pin PD LOW-level input voltage on pin OSC HIGH-input voltage on pin OSC LOW-level output current on pins DB7 to DB0 HIGH-level output current on pins DB7 to DB0 pull-up current on pins DB7 to DB0 leakage current on pins OSC, E, RS, R/W, DB7 to DB0 and SA0 VOL = 0.4 V; VDD = 5 V VOH = 4 V; VDD = 5 V VI = VSS VI = VDD or VSS 0 - 0.3VDD V power-on reset voltage note 3 1.8 2.2 - - - - - 60 45 25 5.5 6.5 120 80 45 V V A A A PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
-
2
6
A
-
1.3
1.6
V
VIH
0.7VDD
-
VDD
V
VIL(PD) VIH(PD) VIL(OSC) VIH(OSC) IOL(DB) IOH(DB) Ipu IL
0 0.8VDD 0
- - -
0.2VDD VDD
V V
VDD - 1.5 V VDD - - 1 +1 V mA mA A A
VDD - 0.1 - 1.6 -1 0.04 -1 4 -8 0.12 -
1998 May 11
33
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
SYMBOL I2C-bus SDA AND SCL VIL VIH IL Ci IOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
LOW-level input voltage HIGH-level input voltage input leakage current input capacitance LOW-level output current pin SDA VI = VDD or VSS note 4 VOL = 0.4 V; VDD = 5 V
0 0.7VDD -1 - 3
- - - - -
0.3VDD 5.5 +1 10 -
V V A pF mA
LCD outputs Ro(ROW) Ro(COL) Vbias(tol) Notes 1. LCD outputs are open-circuit; inputs at VDD or VSS; bus inactive. 2. Tamb = 25 C; fosc = 200 kHz. 3. Resets all logic when VDD < VPOR; 3 oscillator clock cycles required. 4. Tested on sample basis. 5. Resistance of output terminals (R1 to R18 and C1 to C60) with a load current of 20 A; outputs measured one at a time. 6. LCD outputs open-circuit. row output resistance on pins R1 to R18 column output resistance on pins C1 to C60 bias tolerance on pins R1 to R18 and C1 to C60 note 5 note 5 note 6 - - - 10 15 20 30 40 130 k k mV
1998 May 11
34
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
13 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.2 - 6.5 V; Tamb = -40 to +85 C; unless otherwise specified. SYMBOL ffr(LCD) fosc fosc(ext) tOSCST PARAMETER LCD frame frequency (internal clock) oscillator frequency (not available at any pin) external clock frequency oscillator start-up time after PD going from logic 1 to logic 0 CONDITIONS VDD = 5.0 V MIN. 45 140 140 - TYP. 81 250 - 200 MAX. 147 450 450 300 UNIT Hz kHz kHz s
Bus timing characteristics: parallel interface; note 1 WRITE OPERATION (WRITING DATA FROM MICROCONTROLLER TO PCF2103); see Fig.23 Ten(cy) tW(en) tsu(A) th(A) tsu(D) th(D) Ten(cy) tW(en) tsu(A) th(A) td(D) th(D) enable cycle time enable pulse width address set-up time address hold time data set-up time data hold time 500 220 50 25 60 25 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 150 100 ns ns ns ns ns ns
READ OPERATION (READING DATA FROM PCF2103 TO MICROCONTROLLER); see Fig.24 enable cycle time enable pulse width address set-up time address hold time data delay time data hold time 500 220 50 25 - 20 - 1.3 0.6 100 0 - - - 0.6 0.6 0.6 - ns ns ns ns ns ns
Timing characteristics: I2C-bus interface; note 1 fSCL tLOW tHIGH tSU;DAT tHD;DAT tr tf CB tSU;STA tHD;STA tSU;STO tSW Note 1. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. SCL clock frequency SCL clock LOW period SCL clock HIGH period data set-up time data hold time SCL and SDA rise time SCL and SDA fall time capacitive bus line load set-up time for a repeated START condition START condition hold time set-up time for STOP condition tolerable spike width on bus 400 - - - - 300 300 400 - - - 50 kHz s s ns ns ns ns pF s s s ns
1998 May 11
35
Philips Semiconductors
Product specification
LCD controllers/drivers
14 TIMING CHARACTERISTICS
PCF2103 family
handbook, full pagewidth
RS
VIH V IL tsu(A)
VIH VIL th(A) VIL tW(en) th(A) VIL t h(D) DATA VALID Ten(cy) VIH VIL
MGL252
R/W
V IL
E
VIH VIL
VIH VIL tsu(D)
DB0 to DB7
VIH VIL
Fig.23 Parallel bus write operation sequence; writing data from microcontroller to PCF2103.
handbook, full pagewidth
RS
VIH V IL tsu(A)
VIH VIL th(A) VIH
R/W
VIH
tW(en) E VIL VIH VIH VIL t d(D) DB0 to DB7 VOH DATA VOL VALID
th(A) VIL t h(D) VOH VOL
MGL253
Ten(cy)
Fig.24 Parallel bus read operation sequence; reading data from PCF2103 to microcontroller.
1998 May 11
36
Philips Semiconductors
Product specification
LCD controllers/drivers
15 APPLICATION INFORMATION
PCF2103 family
handbook, full pagewidth
P20 P21 P22
RS R/W E
R17, R18
2
R1 to R16
P80CL51
PCF2103
16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGL254
P17 to P10
8
DB7 to DB0
C1 to C60
Fig.25 Direct connection to 8-bit microcontroller; 8-bit bus.
handbook, full pagewidth
P10 P11 P12
RS R/W E
R17, R18
2
R1 to R16
P80CL51
PCF2103
16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
MGL255
P17 to P14
4
DB7 to DB4
C1 to C60
Fig.26 Direct connection to 8-bit microcontroller; 4-bit bus.
handbook, full pagewidth
OSC VDD VLCD 100 nF VSS
R17, R18
2
VDD R1 to R16
PCF2103
VLCD 100 nF VSS
16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
C1 to C60
8 DB7 to DB0 E RS R/W
MGL256
Fig.27 Application example using parallel interface.
1998 May 11
37
Philips Semiconductors
Product specification
LCD controllers/drivers
PCF2103 family
handbook, full pagewidth
VDD VDD
VDD
OSC VDD VLCD 100 nF VSS
DB3/SAO
R17, R18
2
VDD R1 to R16
PCF2103
VLCD 100 nF VSS SCL SDA
16
2 x 12 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
C1 to C60
VSS
OSC VDD VLCD 100 nF VSS
DB3/SAO
R17, R18
2
VDD R1 to R16
PCF2103
VLCD 100 nF VSS SCL SDA
16
1 x 24 CHARACTER LCD DISPLAY PLUS 120 ICONS 60
C1 to C60
SCL SDA
MASTER TRANSMITTER PCF84C81A; P80CL410
MGL257
Fig.28 Application using I2C-bus interface.
1998 May 11
38
Philips Semiconductors
Product specification
LCD controllers/drivers
15.1 4-bit operation, 1-line display using internal reset
PCF2103 family
Since the display shift operation changes display position only and DDRAM contents remain unchanged, display data entered first can be displayed when the `return home' operation is performed. 15.3 8-bit operation, 2-line display
The program must set functions prior to 4-bit operation; Table 11 shows an example. When power is turned on, 8-bit operation is automatically selected and the PCF2103 attempts to perform the first write as an 8-bit operation. Since nothing is connected to DB0 to DB3, a rewrite is then required. However, since one operation is completed in two accesses of 4-bit operation, a rewrite is required to set the functions (see Table 11 step 3). Thus, DB4 to DB7 of the `function set' are written twice. 15.2 8-bit operation, 1-line display using internal reset
For a 2-line display, the cursor automatically moves from the first to the second line after the 40th digit of the first line has been written. Thus, if there are only 8 characters in the first line, the DDRAM address must be set after the eighth character is completed (see Table 6). It should be noted that both lines of the display are always shifted together; data does not shift from one line to the other. 15.4 I2C-bus operation, 1-line display
Table 12 shows an example of a 1-line display in 8-bit operation. The PCF2103 functions must be set by the `function set' instruction prior to display. Since the DDRAM can store data for 80 characters, the RAM can be used for advertising displays when combined with display shift operation.
A control byte is required with most commands (see Table 15).
Table 11 4-bit operation, 1-line display example; using internal reset STEP 1 2 INSTRUCTION power supply on (PCF2103 is initialized by the internal reset circuit) function set RS 0 3 R/W 0 DB7 0 DB6 0 DB5 1 DB4 0 sets to 4-bit operation; in this instance operation is handled as 8-bit by initialization and only this instruction completes with one write sets to 4-bit operation, selects 1-line display and VLCD = V0; 4-bit operation starts from this point and resetting is needed _ turns on display and cursor; entire display is blank after initialization DISPLAY OPERATION initialized; no display appears
function set 0 0 0 0 0 0 0 0 1 0 0 0
4
display on/off control 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 0 _
5
entry mode set 0 0 sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
6
`write data' to CGRAM/DDRAM 1 1 0 0 0 0 1 0 0 0 1 0 P_
1998 May 11
39
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 40 6 7 to 11 `write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_ | | 12 13 14 15 16 `write data' to CGRAM/DDRAM 1 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 1 0 0 1 1 0 1 PHILIPS_ PHILIPS_ HILIPS _ ILIPS | | | M_ writes `S' sets mode for display shift at the time of write entry mode set `write data' to CGRAM/DDRAM writes `H' `write data' to CGRAM/DDRAM writes `M' Philips Semiconductors Table 12 8-bit operation, 1-line display example; using internal reset (character set `A')
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2103 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display
3
display mode on/off control 0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0 P_
PCF2103 family
writes space
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 41 25 return home 0 0 0 0 0 0 0 0 1 0 PHILIPS M returns both display and cursor to the original position (address 0) Philips Semiconductors STEP 17 18 19 20 21 22 23 24 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 INSTRUCTION `write data' to CGRAM/DDRAM 0 0 0 0 0 0 0 0 1 1 0 1 1 0 1 0 0 0 1 0 1 1 0 0 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 0 0 1 MICROKO MICROKO MICROKO ICROKO MICROKO MICROCO_ ICROCOM_ | | | writes `O' shifts only the cursor position to the left shifts only the cursor position to the left writes `C' correction; the display moves to the left shifts the display and cursor to the right shifts only the cursor to the right writes `M' cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM cursor/display shift cursor/display shift `write data' to CGRAM/DDRAM DISPLAY OPERATION
LCD controllers/drivers PCF2103 family
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 42 Philips Semiconductors Table 13 8-bit operation, 1-line display and icon example; using internal reset (character set `A')
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2103 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 _
DISPLAY
OPERATION initialized; no display appears
sets to 8-bit operation, selects 1-line display
3
display mode on/off control 0 turns on display and cursor; entire display is blank after initialization sets mode to increment the address by 1 and to shift the cursor to the right at the time of the write to the DD/CGRAM; display is not shifted sets the CGRAM address to position of character 0; the CGRAM is selected writes data to CGRAM for icon even phase; icons appear | |
4
entry mode set 0 0 0 0 0 0 0 1 1 0 _
5
set CGRAM address 0 0 0 1 0 0 0 0 0 0 _
6 7
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
8
set CGRAM address 0 0 0 1 1 1 0 0 0 0 _ sets the CGRAM address to position of character 4; the CGRAM is selected writes data to CGRAM for icon odd phase |
9 10
`write data' to CGRAM/DDRAM 1 0 0 0 0 0 1 0 1 0 _
PCF2103 family
| 11 12 13 function set 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 0 0 0 0 0 1 0 1 0 1 _ _ _ sets H = 1 icons blink sets H = 0 icon control function set
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 43 Philips Semiconductors STEP 14 set DDRAM address 0 15 0 1 0 0 0 0 0 0 0 sets the DDRAM address to the first position; DDRAM is selected P_ writes `P'; the cursor is incremented by 1 and shifted to the right writes `H' | | 21 return home 0 0 0 0 0 0 0 0 1 0 PHILIPS returns both display and cursor to the original position (address 0) INSTRUCTION DISPLAY OPERATION
LCD controllers/drivers
`write data' to CGRAM/DDRAM 1 0 0 1 0 1 0 0 0 0
16 17 to 20
`write data' to CGRAM/DDRAM 1 0 0 1 0 0 1 0 0 0 PH_
PCF2103 family
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 44 6 to 10 11 12 13 14 to 19 Philips Semiconductors Table 14 8-bit operation, 2-line display example; using internal reset
LCD controllers/drivers
STEP 1 2
INSTRUCTION power supply on (PCF2103 is initialized by the internal reset function) function set RS 0 R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 0 0 0 1 1 1 0 0 0 _ 0 0 0 0 0 0 1 1 1 0 _ 0 0 0 0 0 0 0 1 1 0
DISPLAY
OPERATION initialized; no display appears sets to 8-bit operation; selects 2-line display and voltage generator off
3
display on/off control
turns on display and cursor; entire display is blank after initialization
4
entry mode set
sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the CG/DDRAM; display is not shifted writes `P'; the DDRAM has already been selected by initialization at power-on; the cursor is incremented by 1 and shifted to the right | | |
5
`write data' to CGRAM/DDRAM P_ 1 0 0 1 0 1 0 0 0 0
`write data' to CGRAM/DDRAM PHILIPS_ 1 0 0 1 0 1 0 0 1 1 PHILIPS 0 0 1 1 0 0 0 0 0 0 _ `write data' to CGRAM/ DDRAM PHILIPS 1 0 0 1 0 0 1 1 0 1 M_ | | | set DDRAM address
writes `S'
sets DDRAM address to position the cursor at the head of the 2nd line
PCF2103 family
writes `M'
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 45 Philips Semiconductors STEP 20 INSTRUCTION `write data' to CGRAM/DDRAM PHILIPS 1 21 0 0 1 0 0 1 1 1 1 MICROCO_ sets mode for display shift at the time of write PHILIPS 0 22 0 0 0 0 0 0 1 1 1 MICROCO_ HILIPS 1 23 0 0 1 0 0 1 1 0 1 ICROCOM_ | | | 24 return home PHILIPS 0 0 0 0 0 0 0 0 1 0 MICROCOM returns both display and cursor to the original position (address 0) writes `M'; display is shifted to the left; the first and second lines shift together `write data' to CGRAM/DDRAM `write data' to CGRAM/DDRAM DISPLAY writes `O' OPERATION
LCD controllers/drivers PCF2103 family
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 46 7 8 9 10 Philips Semiconductors Table 15 Example of I2C-bus operation; 1-line display (using internal reset, assuming SA0 = VSS; note 1) STEP 1 2 I2C-bus start INSTRUCTION slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 3 Co 0 4 1 RS 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 Ack 1 selects 1-line display; SCL pulse during acknowledge cycle starts execution of instruction _ 1 1 1 0 1 _ 0 0 1 1 0 1 _ for writing data to DDRAM, RS must be set to 1; therefore a control byte is needed slave address for write SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 Co 0 1 RS 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 _ send a control byte for `write data' Ack 1 writes `P'; the DDRAM has been selected at power-up; the cursor is incremented by 1 and shifted to the right _ sets mode to increment the address by 1 and to shift the cursor to the right at the time of write to the DDRAM or CGRAM; display is not shifted turns on display and cursor; entire display shows character 20H (blank in ASCII-like character sets) send a control byte for `function set' control byte sets RS for following data bytes during the acknowledge cycle SDA will be pulled-down by the PCF2103 DISPLAY OPERATION initialized; no display appears
LCD controllers/drivers
function set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 1 X 0 0 0 0 1
5
display on/off control DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0
6
entry mode set DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0
I2C-bus start
PCF2103 family
Product specification
`write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 1 0 0 0 0 1 P_
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 47 Philips Semiconductors STEP 11 INSTRUCTION `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 12 to 15 1 0 0 1 0 0 0 1 PH_ | | | | 16 `write data' to DDRAM DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 17 18 1 0 1 0 0 1 1 1 PHILIPS_ PHILIPS_ (optional I2C-bus stop) I2C-bus start + slave address for write (as step 8) control byte Co 1 19 RS 0 0 0 0 0 0 0 0 0 0 0 0 0 Ack 1 PHILIPS_ sets DDRAM address 0 in address counter (also returns shifted display to original position; DDRAM contents unchanged); this instruction does not update the Data Register (DR) writes `S' writes `H' DISPLAY OPERATION
LCD controllers/drivers
return home DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 0 0 0 0 0 1 0 1 PHILIPS PHILIPS during the acknowledge cycle the content of the DR is loaded into the internal I2C-bus interface to be shifted out; in the previous instruction neither a `set address' nor a `read data' has been performed; therefore the content of the DR was unknown; R/W has to be set to logic 1 while still in I2C-bus write mode DDRAM content will be read from following instructions PHILIPS
20 21
I2C-bus start slave address for read SA6 SA5 SA4 SA3 SA2 SA1 SA0 R/W Ack 0 1 1 1 0 1 0 1 1
PHILIPS
PCF2103 family
22
control byte for read Co 0 RS 1 0 1 0 0 0 0 0 0 0 0 0 0 Ack 1
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 48 Philips Semiconductors STEP 23 INSTRUCTION `read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack X X X X X X X X 0 PHILIPS 8 x SCL; content loaded into interface during previous acknowledge cycle is shifted out over SDA; MSB is DB7; during master acknowledge content of DDRAM address 01 is loaded into the I2C-bus interface 8 x SCL; code of letter `H' is read first; during master acknowledge code of `I' is loaded into the I2C-bus interface no master acknowledge; after the content of the I2C-bus interface register is shifted out no internal action is performed; no new data is loaded to the interface register, Data Register (DR) is not updated, Address Counter (AC) is not incremented and cursor is not shifted DISPLAY OPERATION
LCD controllers/drivers
24
`read data': 8 x SCL + master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 0 0 PHILIPS
25
`read data': 8 x SCL + no master acknowledge; note 2 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Ack 0 1 0 0 1 0 0 1 1 PHILIPS
26 Notes
I2C-bus stop
PHILIPS
1. X = don't care. 2. SDA is left at high-impedance by the microcontroller during the read acknowledge.
PCF2103 family
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 49 Philips Semiconductors Table 16 Initialization by instruction, 8-bit interface (note 1)
LCD controllers/drivers
STEP power-on or unknown state | wait 2 ms after VDD rises above VPOR | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait 2 ms | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | wait more than 40 s | RS 0 R/W 0 DB7 0 DB6 0 DB5 1 | | RS 0 0 0 0 R/W 0 0 0 0 DB7 0 0 0 0 DB6 0 0 0 0 DB5 1 0 0 0 | Initialization ends Note 1. X = don't care. DB4 1 0 0 0 DB3 0 1 0 0 DB2 M 0 0 1 DB1 0 0 0 I/D DB4 1 DB3 X DB2 X DB1 X DB4 1 DB3 X DB2 X DB1 X DB4 1 DB3 X DB2 X DB1 X
DESCRIPTION
DB0 BF cannot be checked before this instruction X function set (interface is 8 bits long)
DB0 BF cannot be checked before this instruction X function set (interface is 8 bits long)
DB0 BF cannot be checked before this instruction X function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 4) DB0 function set (interface is 8 bits long); specify the number of display lines H 0 1 S display off clear display entry mode set
PCF2103 family
Product specification
This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 1998 May 11 50 Philips Semiconductors Table 17 Initialization by instruction, 4-bit interface; not applicable for I2C-bus operation
LCD controllers/drivers
STEP Power-on or unknown state | Wait 2 ms after VDD rises above VPOR | RS 0 Wait 2 ms | RS 0 Wait 40 s | RS 0 R/W 0 DB7 0 | RS 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 0 0 DB7 0 0 0 0 1 0 0 0 0 | Initialization ends DB6 0 0 M 0 0 0 0 0 1 DB5 1 1 0 0 0 0 0 0 I/D DB4 0 0 H 0 0 0 1 0 S entry mode set display off DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1 R/W 0 DB7 0 | DB6 0 DB5 1 DB4 1
DESCRIPTION
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long)
BF cannot be checked before this instruction function set (interface is 8 bits long) BF can be checked after the following instructions; when BF is not checked, the waiting time between instructions is the specified instruction time (see Table 4) function set (set interface to 4 bits long) interface is 8 bits long function set (interface is 4 bits long) specify number of display lines
PCF2103 family
clear display
Product specification
Philips Semiconductors
Product specification
LCD controllers/drivers
16 BONDING PAD LOCATIONS
PCF2103 family
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
C3
C4
C5
C6
C7
C8
78 77 76 75 74 73 72 71 70
C9
handbook, full pagewidth
69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
C27
C27(dummy)
C3(dummy)
C2(dummy) C2 C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 3.18 mm SCL SDA E RS R/W DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB0(dummy)
79 80 81 82 83 84 85 86 87 88 89 90 91 92
C28(dummy) C28 C29 C30 C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C52(dummy)
PCF2103-2 C53(dummy)
ROM xxx
50 49 48 47 46 45 44 43 42 41 40 39
x 0 0 y
38 37 36
93 94 95 96 97 98 99 100 101 102 103 104 105 1 2 3 4 5 6 7 8
35 34 33 32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
VDD(dummy)
VDD OSC
PD
T1
VSS
VLCD
R9
R10
R11
R12
R13
R14
R15
R16
R18
C60
C59
C58
C57
C56
C55
C54
2.99 mm
C53
MGL258
Fig.29 Bonding pad locations.
1998 May 11
51
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 18 Bonding pad locations (dimensions in m). All x/y coordinates are referenced to centre of chip (see Fig.29) SYMBOL VDD (dummy) VDD OSC PD T1 VSS VLCD R9 R10 R11 R12 R13 R14 R15 R16 R18 C60 C59 C58 C57 C56 C55 C54 C53 C53 (dummy) C52 (dummy) C52 C51 C50 C49 C48 C47 C46 C45 C44 C43 C42 C41 1998 May 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 PAD 105 X -1228 -1048 -958 -868 -778 -688 -516 -349 -259 -169 -79 11 101 191 281 371 461 551 641 731 821 911 1001 1091 1181 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 Y -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1414 -1254 -1164 -1074 -948 -812 -722 -632 -542 -452 -362 -272 -182 -92 52 SYMBOL C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C28 (dummy) C27 (dummy) C27 C26 C25 C24 C23 C22 C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 PAD
PCF2103 family
X 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1344 1262 1172 1082 992 902 805 715 625 535 445 355 265 175 85 -5 -95 -185 -275 -446 -536 -626 -716 -806 -896 -2 88 178 268 358 448 538 628 718 808 898 1070 1160 1250 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414 1414
Y
Philips Semiconductors
Product specification
LCD controllers/drivers
Table 19 Bump specifications PARAMETER Bump variant Type Bump width Bump length Bump height Height difference in one die Convex deformation Pad size; aluminium Wafer thickness Minimum pitch
PCF2103 family
SYMBOL C4 C3 C3 (dummy) C2 (dummy) C2 C1 R8 R7 R6 R5 R4 R3 R2 R1 R17 SCL SDA E RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB0 (dummy) Rec. Pat. C1 Rec. Pat. C2 Rec. Pat. F 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
PAD -986
X 1414 1414 1414 1303 1213 1123 1033 943 853 763 673 583 493 403 313 131 -9 -195 -289 -382 -476 -572 -668 -765 -861 -957 -1076 -1166 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 -1344 1335 -1335 -1340
Y
SPECIFICATION N galvanic; pure aurum 60 6 90 6 17.5 5 <2 <5 80 x 100 380 25 90
UNIT - - m m m m m m m m m
Passivation opening CBB 46 x 76
100 101 102 103 104
-1054 -1150 -1240 -1405 1405 -1397
1998 May 11
53
Philips Semiconductors
Product specification
LCD controllers/drivers
17 DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
PCF2103 family
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. 18 LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 19 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
1998 May 11
54
Philips Semiconductors
Product specification
LCD controllers/drivers
NOTES
PCF2103 family
1998 May 11
55
Philips Semiconductors - a worldwide company
Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. Box 213, Tel. +43 160 1010, Fax. +43 160 101 1210 Belarus: Hotel Minsk Business Center, Bld. 3, r. 1211, Volodarski Str. 6, 220050 MINSK, Tel. +375 172 200 733, Fax. +375 172 200 773 Belgium: see The Netherlands Brazil: see South America Bulgaria: Philips Bulgaria Ltd., Energoproject, 15th floor, 51 James Bourchier Blvd., 1407 SOFIA, Tel. +359 2 689 211, Fax. +359 2 689 102 Canada: PHILIPS SEMICONDUCTORS/COMPONENTS, Tel. +1 800 234 7381 China/Hong Kong: 501 Hong Kong Industrial Technology Centre, 72 Tat Chee Avenue, Kowloon Tong, HONG KONG, Tel. +852 2319 7888, Fax. +852 2319 7700 Colombia: see South America Czech Republic: see Austria Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. +45 32 88 2636, Fax. +45 31 57 0044 Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. +358 9 615800, Fax. +358 9 61580920 France: 51 Rue Carnot, BP317, 92156 SURESNES Cedex, Tel. +33 1 40 99 6161, Fax. +33 1 40 99 6427 Germany: Hammerbrookstrae 69, D-20097 HAMBURG, Tel. +49 40 23 53 60, Fax. +49 40 23 536 300 Greece: No. 15, 25th March Street, GR 17778 TAVROS/ATHENS, Tel. +30 1 4894 339/239, Fax. +30 1 4814 240 Hungary: see Austria India: Philips INDIA Ltd, Band Box Building, 2nd floor, 254-D, Dr. Annie Besant Road, Worli, MUMBAI 400 025, Tel. +91 22 493 8541, Fax. +91 22 493 0966 Indonesia: PT Philips Development Corporation, Semiconductors Division, Gedung Philips, Jl. Buncit Raya Kav.99-100, JAKARTA 12510, Tel. +62 21 794 0040 ext. 2501, Fax. +62 21 794 0080 Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. +353 1 7640 000, Fax. +353 1 7640 200 Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053, TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007 Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3, 20124 MILANO, Tel. +39 2 6752 2531, Fax. +39 2 6752 2557 Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku, TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077 Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL, Tel. +82 2 709 1412, Fax. +82 2 709 1415 Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR, Tel. +60 3 750 5214, Fax. +60 3 757 4880 Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905, Tel. +9-5 800 234 7381 Middle East: see Italy Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB, Tel. +31 40 27 82785, Fax. +31 40 27 88399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, Tel. +64 9 849 4160, Fax. +64 9 849 7811 Norway: Box 1, Manglerud 0612, OSLO, Tel. +47 22 74 8000, Fax. +47 22 74 8341 Pakistan: see Singapore Philippines: Philips Semiconductors Philippines Inc., 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Metro MANILA, Tel. +63 2 816 6380, Fax. +63 2 817 3474 Poland: Ul. Lukiska 10, PL 04-123 WARSZAWA, Tel. +48 22 612 2831, Fax. +48 22 612 2327 Portugal: see Spain Romania: see Italy Russia: Philips Russia, Ul. Usatcheva 35A, 119048 MOSCOW, Tel. +7 095 755 6918, Fax. +7 095 755 6919 Singapore: Lorong 1, Toa Payoh, SINGAPORE 319762, Tel. +65 350 2538, Fax. +65 251 6500 Slovakia: see Austria Slovenia: see Italy South Africa: S.A. PHILIPS Pty Ltd., 195-215 Main Road Martindale, 2092 JOHANNESBURG, P.O. Box 7430 Johannesburg 2000, Tel. +27 11 470 5911, Fax. +27 11 470 5494 South America: Al. Vicente Pinzon, 173, 6th floor, 04547-130 SAO PAULO, SP, Brazil, Tel. +55 11 821 2333, Fax. +55 11 821 2382 Spain: Balmes 22, 08007 BARCELONA, Tel. +34 93 301 6312, Fax. +34 93 301 4107 Sweden: Kottbygatan 7, Akalla, S-16485 STOCKHOLM, Tel. +46 8 5985 2000, Fax. +46 8 5985 2745 Switzerland: Allmendstrasse 140, CH-8027 ZURICH, Tel. +41 1 488 2741 Fax. +41 1 488 3263 Taiwan: Philips Semiconductors, 6F, No. 96, Chien Kuo N. Rd., Sec. 1, TAIPEI, Taiwan Tel. +886 2 2134 2865, Fax. +886 2 2134 2874 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., 209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260, Tel. +66 2 745 4090, Fax. +66 2 398 0793 Turkey: Talatpasa Cad. No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 Internet: http://www.semiconductors.philips.com
For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1998
SCA60
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
415106/1200/01/pp56
Date of release: 1998 May 11
Document order number:
9397 750 02649

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